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Semiconductor MSM58321
Semiconductor REAL TIME CLOCK/CALENDAR DESCRIPTION
The MSM 58321 is a metal gate CMOS Real Time Clock/Calendar with a battery backup function for use in bus-oriented microprocessor applications. The 4-bit bidirectional bus line method is used for the data I/O circuit; the clock is set, corrected, or read by accessing the memory.
MSM58321
The time is read with 4-bit DATA I/O, ADDRESS WRITE, READ, and BUSY; it is written with 4-bit DATA I/O, ADDRESS WRITE, WRITE, and BUSY.
FEATURES
* 7 Function-Second, Minute, Hour, Day, Day-of-Week, Month, Year * Automatic leap year calender * 12/24 hour format * Frequency divider 5-poststage reset * Reference signal output * * * * 32.768 kHz crystal controlled operation Single 5V power supply Back-up battery operation to VDD = 2.2V Low power dissipation 90 W max. at VDD = 3V 2.5 mW max. at VDD = 5V * 16 pin plastic DIP (DIP 16-P-300)
FUNCTIONAL BLOCK DIAGRAM
5-poststage (O11~O15) XT XT BUSY N STOP Rp TEST Rp WRITE Rp READ Rp CS1 Rp CS2 Rp D0 D1 D2 D3 TRI-STATE CONTROL ADDRESS LATCH ADDRESS DECODER
0 1 2 3 4 5 6 7 8 9 A B C D E-F S1 S10 MI1 MI10 H1 H10 W D1 D10 MO1 MO10 Y1 Y10 D E-F
1024 Hz 1 Hz 1/60 Hz 1/3600 Hz \DATA BUS 4 E-F 4 SWITCH S1 S10 1/10 1/6 3 4 MI1 MI10 1/10 1/6 MINUTE 3 H1 H10
1/12 or 1/24 W 1/7 WEEK
RFB
1
OSC
215
R
BUSY R
4
3
TEST D WRIETE 1 Hz WRITE S1 S10 MI1 MI10 H1 H10 W SECOND HOUR
READ CS 4 D1 D10 1/10 1/3 DAY WRITE
D1 D10 MO1 MO10 Y1 Y10
DATA BUS
TEST-P
4
4
MO1 MO10
4 Y1 Y10 1/10 1/10 YEAR
4
1/12 MONTH
Rp = 200 k TYP
ADDRESS WRITE Rp
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MSM58321 PIN CONFIGURATION
16 pin Plastic DIP (top View) CS2 1 16 VDD 15 XT 14 XT 13 CS1 12 TEST 11 STOP 10 BUSY
Semiconductor
WRITE 2 READ D0 D1 D2 D3 GND 3 4 5 6 7 8
9 ADDRESS WRITE
REGISTER TABLE
Address input Address D0 (A0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D1 (A1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D2 (A2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 D3 (A3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Register Name D0 S1 S10 MI1 MI10 H1 H10 W D1 D10 MO1 MO10 Y1 Y10 * * * * * * * * * * * * * * * * * * * Data input/ output Count value D1 D2 * * * * * * * * * * * * * * * * * * * * * * * * * * D3 * 0 0 0 0 0 to to to to to 9 5 9 5 9 Remarks
0 1 2 3 4 5 6 7 8 9 A B C D
D2 = 1 specifies PM, D2 = 0 specifies AM, D3 = 1 specifies 24-hour timer, and 0~1 or 0~2 D3 = 0 specifies 12-hour timer. When D3 = 1 is written, the D2 bit is reset inside the IC. 0 0 0 0 0 0 0 to to to to to to to 6 9 3 9 1 9 9 The D2 and D3 bits in D10 are used to select a leap year. Remainder obtained by dividing the Calendar D 2 D3 year number by 4 Gregorian calendar 0 0 0 10 3 01 2 11 1 A selector to reset 5 poststages in the 1/215 frequency divider and the BUSY circuit. They are reset when this code is latched with ADDRESS LATCH and the WRITE input goes to 1. A selector to obtain reference signal output. Reference signals are output to D0 - D3 when this code is latched with ADDRESS LATCH and READ input goes to 1.
E~F
0/1
1
1
1
Note:
(1) (2) (3)
There are no bits in blank fields for data input/output. 0 signals are output by reading and data is not stored by writing because there are no bits. The bit with marked * is used to select the 12/24-hour timer and the bits marked * are used to select a leap year. These three bits can be read or written. When signals are input to bus lines D0 - D3 and ADDRESS WRITE goes to 1 for address input, ADDRESS information is latched with ADDRESS LATCH.
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Semiconductor ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating Power voltage Input voltage Output voltage Storage temperature Symbol VDD VI VO Tstg Condition Ta = 25C Ta = 25C Ta = 25C - Value
MSM58321
Unit V V V C
-0.3 to 6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150
Operating Conditions
Rating Power voltage Date hold voltage Crystal frequency Operating temperature Note: Symbol VDD VDH (XT) TOP Condition - - - - Value 4.5 to 6 2.2 to 6 32.768 -30 to +85 Unit V V kHz C
The data hold voltage guarantees the clock operations, though it does not guarantee operations outside the IC and data input/output.
DC Characteristics
(VDD = 5V 5%, Ta = -30 ~ +85C) Rating H input voltage L input voltage L output voltage L output current H input current L input current Input capacity Current consumption Note: Symbol VIH1 VIH2 VIL VOL IOL IIH1 IIH2 IIL CI IDD Condition - Note 1 - Note 2 - IO = 1.6 mA VO = 0.4 V VI = VDD Note3 VI = VDD Note4 VI = 0V = 1 MHz = 32.768 kHz VDD = 5V/VDD = 3V Min. 3.6 VDD-0.5 - - 1.6 10 - - - - Typ. - - - - - 30 - - 5 100/15 Max. - - 0.8 0.4 - 80 1 -1 - 500/30 A pF A Unit V V V mA A
1. 2. 3. 4.
CS2, WRITE, READ, ADDRESS WRITE, STOP, TEST, D0 ~ D3 CS1 CS1, CS2, WRITE, READ, ADDRESS WRITE, STOP, TEST D0 ~ D3
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MSM58321 Switching Characteristics
(1) WRITE mode
Semiconductor
(VDD = 5V 5%, Ta = 25C) Rating CS setup time CS hold time Address setup time Address write pulse width Address hold time Data setup time Write pulse width Data hold time Symbol tCS tCH tAS tAW tAH tDS tWW tDH Condition - - - - - - - - Min. 0 0 0 0.5 0.1 0 2 0 Typ. - - - - - - - - Max. - - - - - - - - Unit s s s s s s s s
CS1 CS2 D0 ~ D3 (ADDRESS/DATA) ADDRESS WRITE
,, ,,
H L
,, ,, ,, ,,
tCS
tAS
tAW tAH tDS tWW tDH
tCH
,,
,,
,, High ,Impedance ,, , ,
,,
,,
WRITE
,
IC internal ADDRESS IC internal DATA
ADDRESS
DATA
Write Cycle Note: ADDRESS WRITE and WRITE inputs are activated by the level, not by the edge.
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Semiconductor
(2) READ mode
MSM58321
(VDD = 5V 5%, Ta = 25C) Rating CS setup time CS hold time Address setup time Address write pulse width Address hold time Read access time Read delay time Read inhibit time Note 1. tRA = 1 s + CR ln ( Symbol tCS tCH tAS tAW tAH tRA tDD tRI VDD ) VDD - VIH min Condition - - - - - - - - Min. 0 0 0 0.5 0.1 - - 0 Typ. - - - - - - - - Max. - - - - - see Note 1 1 - Unit s s s s s s s s
CS1 CS2 D0 ~ D3 (ADDRESS/DATA)
,,
H L tCS tAS tAW tRH
tRI tRA
DATA VALID tDD
DATA INVALID
,, ,, ,, ,, ,, , ,, ,, ,, ,, ,, ,,
tCH
,, ,, ,, ,, ,
,,
, ,,
ADDRESS WRITE READ
High Impedance
,, ,, ,, ,
ADDRESS
DATA
Read Cycle
Note: ADDRESS WRITE and READ inputs are activated by the level, not by the edge.
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MSM58321
(3) WRITE & READ mode
Semiconductor
(VDD = 5V 5%, Ta = 25C) Rating CS setup time CS hold time Address setup time Address write pulse width Address hold time Data setup time Write pulse width Data hold time Read access time Read delay time Read inhibit time Note 1. tRA = 1 s + CR ln ( Symbol tCS tCH tAS tAW tAH tDS tWW tDH tRA tDD tRI VDD ) VDD - VIH min Condition - - - - - - - - - - - Min. 0 0 0 0.5 0.1 0 2 0 - - 0 Typ. - - - - - - - - - - - Max. - - - - - - - - see Note 1 1 - Unit s s s s s s s s s s s
DATA INVALID DATA VALID H L tCS tAS tAW tAH tDS tWW tDH
,, ,, ,,
CS1 CS2 D0 ~ D3 (ADDRESS/DATA)
tRI tRA
,, ,, ,,
tDD tCH ,
ADDRESS WRITE ,,,,,, WRITE READ IC internal ADDRESS IC internal DATA
,,
,
,,
,,
High Impedance
,, ,
,,
,,
,,
ADDRESS
DATA WRITE
DATA READ
Read & Write Cycle
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Semiconductor PIN DESCRIPTION
Name CS2 Pin No. 1 Description
MSM58321
Chip select pins. These pins enable the interface with the external circuit when both of these pins are set at H level simultaneously. If one of these pins is set at L level, STOP, TEST, WRITE, READ, ADDRESS WRITE pins and D0 ~ D3 pins are inactivated. Since the threshold voltage VT for the CS1 pin is higher than that for other pins, it shuold be connected to the detector of power circuit and peripherals and CS2 is to be connected to the microcontroller. WRITE pin is used to write data; it is activated when it is at the H level. Data bus data inside the IC is loaded to the object digit while this WRITE pin is at the H level, not at the WRITE input edge. Refer to Figure 1 below.
CS1
13
WRITE
2
(S1 digit) D0 Q S R S D3 Q R
WRITE D0 D1 D2 D3 S1 CS1 = CS2 = "H" D0 H S1 WRITE F/F D0- Figure 1 DATA BUS
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MSM58321
Name READ Pin No. 3 Description
Semiconductor
READ pin is used to read data; it is activated when it is at the H level. Address contents are latched with ADDRESS LATCH inside the IC at the D0 ~ D3 and ADDRESS WRITE pins to select the object digit, then an H-level signal is input to the READ pin to read data. If a count operation is continued by setting the STOP input to the L level, read operation must be performed, in principle, while the BUSY output is at the H level. While the BUSY output is at the L level, count operations are performed by digit counters and read data is not guaranteed, therefore, read operations are inhibited in this period. Figure 2 shows a time chart of the BUSY output, 1 Hz signal inside the IC, and READ input. A read operation is stopped temporarily within a period of 244 s from the BUSY output trailing edge and it is restarted when the BUSY output goes to the H level again.
427 s BUSY The counter inside the IC starts counting at the 1 Hz signal leading edge. Read-enabled period 244 s 122 s 61 s
1 Hz (inside IC) Read-enabled period
Read-inhibited period Read operation is enabled in this period: however, it is used for program switching.
BUSY
1 Hz (inside IC)
READ input
1 sec
Figure 2
If the counter operation is stopped by setting the STOP input to the H level, read operations are enabled regardless of the BUSY output. A read operation is enabled by microcomputer software regardless of the BUSY output during the counter operation by setting the STOP input to the L level. In this method, read operations are performed two or more times continuously and data that matches twice is used as guaranteed data.
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Semiconductor
Name D0 ~ D3 Pin No. 4~7 Description
MSM58321
Data input/output pins. (Bidirectional bus). The output is a open-drain type and 4.7 k ~ 10 k pull-up registers are required utilize these pins as output pins. Ground pin. ADDRESS WRITE pin is used to load address information from the D0 ~ D3 I/O bus pins to the ADDRESS LATCH inside the IC; it is activated when it is at the H level. This input is activated by the level, not by the edge. Figure 3 shows the relationships between the D0 address input, ADDRESS WRITE input, and ADDRESS LATCH input/output.
D0 input
GND ADDRESS WRITE
8 9
ADDRESS WRITE DI0 ADDRESS LATCH (inside IC) L DO0 LATCH output
Figure 3 BUSY 10 BUSY pin outputs the IC operation state. It is N-channel MOSFET open-drain output. An external pull-up resistor of 4.6 k or more must be connected (see Figure 4) to use the BUSY output. The signals are output in negative logics. If the oscillator oscillates at 32.768 kHz, the frequency is always 1 Hz regardless of the CS1 and CS2 unless the D output of the ADDRESS DECODER inside the IC is H (CODE = H*L*H*H) and CS1 = CS2 = WRITE = H. Figure 5 shows the BUSY output time chart.
(peripheral circuit power) 4.7 k or more +5V BUSY BUSY RESET N MSM58321RS D
WRITE
Figure 4
BUSY The counter inside the IC starts counting at the 1 Hz signal leading edge.
1 Hz (inside IC)
244 s 122 s 61 s 427 s Read/write-inhibited period
BUSY
1 Hz (inside IC)
1 sec
Figure 5
15
MSM58321
Name STOP Pin No. 11 Description
Semiconductor
The STOP pin is used to input on/off control for a 1 Hz signal. When this pin goes to the H level, 1 Hz signals are inhibited and counting for all digits succeeding the S1 digit is stopped. When this pin goes to the L level, normal operations are performed; the digits are counted up. This STOP input controls stopping digit counting. Writing of external data in digits can be assured by setting the STOP input to the H level to stop counting, then writing sequentially from the low-order digits. The TEST pin is used to test this IC; it is normally open or connected to GND. It is recommended to connect it to GND to safeguard against malfunctions from noise. The TEST pulse can be input to the following nine digits: S1, S10, MI10, H1, D1 (W), M01, Y1 and Y10 When a TEST pulse is input to the D1 digit, the W digit is also counted up simultaneously. Input a TEST pulse as follows: Set the address to either digit explained above, then input a pulse to the TEST pin while CS1 = CS2 = STOP = H and WRITE = L. The specified and succeeding digits are counted up. (See Figure 6)
0~9 1 Hz C1 C10 S1 C10 S10 C10 MI1 0~5 0~9
TEST
12
TEST
Rp C-S S1 0~9
TEST-P S10 0~6 C0 D1 C1 W C1 D10 MI1
D1
Rp = 200 k TYP
Figure 6
A digit is counted up at the leading edge (changing point from L to H) of a TEST pin input pulse. The pulse condition for TEST pin input at VDD = 5V 5% is described in Figure 7 below.
tH
tL tH = 10 s MIN
tL = 10 s MIN
Figure 7
16
Semiconductor
Name XT XT Pin No. 14 15 Description
MSM58321
Oscillator pin. A 32.768 kHz crystal oscillator, capacitor and trim capacitor for frequency adjustment are to be connected as shown in Figure 8 below.
XT C1 GND or VDD C2 XT RFB RS MSM58321
RFB = 10 M TYP RS = 200 k typ
X-TAL 32.768 kHz, The crystal impedance is 30 k or less.
Figure 8
If an external clock is to be used for MSM58321's oscillation source, the external clock is to be input to XT, while XT should be left open. Refer to the Figure 9 below.
CMOS XT
or
+5V XT MSM58321
TTL
Figure 9
VDD
16
Power supply pin. Refer to the application circuit.
17
MSM58321
Semiconductor
REFERENCE SIGNAL OUTPUT
Reference signals are output from the D0 ~ D3 pins under the following conditions: Conditions WRITE = L READ = H CS1 = CS2 = H ADDRESS = E or F Output pin D0 D1 D2 D3 Reference signal frequency 1024 Hz 1 Hz 1/60 Hz 1/3600 Hz Pulse width 488.3 s 122.1 s 122.1 s 122.1 s Output logic Pisitive logic Negative logic Negative logic Netgative logic
488.3 s 1024 Hz 1 Hz 1/60 Hz 1/3600 Hz
488.3 s
1 Hz (inside IC) BUSY
244 s
122 s 61 s
-3 122.1 s = 10 x4 32,768 -3 488.3 s = 10 x16 32,768
Figure 10
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Semiconductor APPLICATION NOTES
WRITE and STOP
MSM58321
Note that the timing relationship between the STOP and WRITE inputs vary by the related digit when counting is stopped by the STOP input to write data. The time (tSH) between the STOP input leading edge and WRITE input trailing edge for each digit is limited to the minimum value. (See Figure 11)
at VDD = 5V5% STOP S1 WRITE 1 tSHS1 tSHS10 tSHY10 Write-inhibited period S10 2 MI1 3 MI10 4 H1 5 H10 D1(W) D10 6 7 8 MO1 MO10 9 10 Y1 11 Y10 12
Figure 11 tSHS1 = 1 s, tSHS10 = 2 s, tSHMI1 = 3 s, tSHM10 = 4 s, tSHH1 = 5 s tSHH10 = 6 s, tSHD1 = 7 s, tSHW = 7 s, tSHD10 = 8 s, tSHM01 = 9 s tSHMO10 = 10 s, tSHY1 = 11 s, tSHY10 = 12 s.
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MSM58321
Semiconductor
If a count operation is continued by setting the STOP input to the L level, write operation must be performed, in principle, while the BUSY output is at the H level. While the BUSY output is at the L level, count operations are performed by the digit counters and write operation is inhibited, but there is a marginal period of 244 s from the BUSY output trailing edge. If the BUSY output goes to the L level during a write operation, the write operation is stopped temporarily within 244 s and it is restarted when the BUSY output goes to the H level again. Figure 12 shows a time chart of BUSY output, 1 Hz signal inside the IC, and WRITE input.
BUSY
1 Hz (inside IC) WRITE input 1 sec
Figure 12
Frequency divider and BUSY circuit reset
If A0 ~ A3 = H*L*H*H is input to ADDRESS DECODER, the DECODER output (D) goes to the H level. If CS1 = CS2 = H and WRITE = H in this state, the 5 poststage in the 15-stage frequency divider and the BUSY circuit are reset. In this period, the BUSY output remains at the H level and the 1 Hz signal inside the IC remains at the L level, and counting is stopped. If this reset is inactivated while the oscillator operates, the BUSY output goes to the L level after 1000.1221 31.25 ms and the 1 Hz signal inside the IC goes to the H level after 1000.3663 31.25 ms. These times are not the same because the first ten stages in the 15-stage frequency divider are not reset. (See Figure 13)
15-stage frequency divider circuit 32,768 kHz BUSY N STOP Rp WRITE Rp CS D From ADDRESS DECODER A0 A1 A2 A3 HLHH t3 O15 (inside IC) WRITE RESET STOP OSC 1~10 stage
Stages 11~15 015 R BUSY R 1 Hz
1 Hz (inside IC) RESET (inside IC) t1 = 1000.1221 31.25 ms t2 = 1000.3663 31.25 ms t3 = 1000 31.25 ms t1 t2
Figure 13
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Semiconductor
Selection of leap year
This IC is designed to select leap year automatically.
MSM58321
Four types of leap years can be selected by writing a select signal in the D2 and D3 bits of the D10 digit (CODE = L*L*L*H). (See table 1 for the functions.) Gregorian calendar or other calendars can be set arbitrarily in the Y1 and Y10 digits of this IC. There is a leap year every four years and the year number varies according to the calendar used. There are four combinations of year numbers and leap years. (See the Table below). No. 1: No. 2: No. 3: No. 4:
No.1 1
Gregorian calendar year. The remainder obtained by dividing the leap year number by 4 is 0. The remainder obtained by dividing the leap year number by 4 is 3. The remainder obtained by dividing the leap year number by 4 is 2. The remainder obtained by dividing the leap year number by 4 is 1.
Calendar Gregorian L D10 digit D2 D3 L Remainder obtained by dividing the leap year number by 4 0 Leap years (examples) 1980, 1984, 1988, 1992 1996, 2000, 2004 (83) (87) (91) (95) (99) 55, 59, 63, 67, 71, 75, 79 82, 86, 90, 94, 98, 102, 106 81, 85, 89, 93, 97, 101, 105
2
H
L
3
3 4
L H
H H
2 1
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MSM58321
Semiconductor
APPLICATION EXAMPLE - POWER SUPPLY CIRCUIT
VF = 0.69V 1S1588 +5.7V 100 a) + or C372 GND MSM58321 VF = 0.69 1.2x3 = 3.6V Ni-Cd battery - + 4.7 VDD Backup 0 mV Operating state 20 mV P-P Ripple
VCE (Sat) = 0.1V A495 100 51K b) C372 10K + - 10K + - 4.7
Ripple Operating state VDD Backup 20 mV P-P 0 mV
GND MSM58321
+5V RL
RL MC B +
100 4.7 VDD
+ -
c)
- GND MSM58321 1.5x2 = 3V Dry cell
(Recommended circuit) +V (Power voltage approximately 1.5V higher than 5V) d) D1 +5V (Peripheral circuit power) R2 100 + - 3.6V Ni-Cd battery GND MSM58321 4.7 D2
VDD
Note: Use the same diodes for D1 and D2 to reduce the level difference between +5V and VDD of the MSM58321.
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